Community Newsletter: Special DVCon Edition
IN THIS ISSUE:
- DVCon Grows in the Global Community
Adam Sherer talks DVCon expansion, regional growth
- Spotlight: DVCon India
September 25-26, Bangalore, India
- Spotlight: DVCon Europe
October 14-15, Munich, Germany
- Upcoming: DVCon United States
March 2-5, San Jose, California
by Adam Sherer, Accellera Promotions Committee Chair
"Yes, I can make that better" is the mantra that we, the world’s engineers, translate into the efficiency and innovation that drives continuous product improvements in our companies. Accellera has tapped that energy to create a positive feedback loop between our standards development and the technology envelope presented annually by all of you at the Design and Verification Conference (DVCon). Following our mantra, we are making DVCon better by growing into the global community.
Each year DVCon United States draws hundreds of people to learn about standards, present technical concepts and accomplishments, and socialize new ideas. For example, the gravitational attraction of ideas and people in this environment in 2008 ignited the working group that led to UVM. Recognizing that we can all benefit from more breakthroughs like this, we are growing the DVCon environment into the global community starting with India and Europe this year.
Both the Europe and India events continue the expert-to-expert connection and deep technical discussions that make the DVCon experience directly applicable to your daily work. Take a look through the agendas for each event and you’ll surely find technology that motivates you. Then, follow the links to sign up and attend the event in your region. With our "yes, I can make that better" mantra in these new DVCon events, we will share ideas and seed new standards that drive efficiency and innovation. Welcome to the global DVCon events!
September 25-26, 2014
DVCon India presents an excellent platform to share knowledge, experience and best practices covering electronic system level design & verification for IP and SOC, VIP development and virtual prototyping for embedded software development and debug.
The two-day conference provides multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions and exhibits from ecosystem partners. In addition, attendees will get the latest information on Accellera standards for system design, modeling and verification.
We encourage you to register early, as Early Registration ends September 15 and space and seating is limited.
Keynote Speaker: Walden C. Rhines
Chief Executive Officer and Chairman of the Board of Director
"Accelerating EDA Innovation Through SoC Design Methodology Convergence"
Every two years, the Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. Results of the most recent survey demonstrate an ongoing convergence of SoC design practices toward a common methodology, independent of the specific tools being used. This type of methodology standardization normally drives the EDA industry into a productive wave of innovation, as EDA companies develop a variety of new tools to optimize results achieved with a standard methodology. In this keynote, Rhines identifies the common attributes of SoC methodology that are emerging, and then highlights specific capability enablers for the further optimization of SoC design verification. View bio >
Keynote Speaker: Dr. Mahesh Mehendale
MCU Chief Technologist and Director of Kilby Labs India
"Challenges in the Design and Verification of Ultra-low Power 'More than Moore' Systems"
While the "more of Moore" journey of CMOS technology scaling continues, enabling higher levels of digital logic integration, there are many electronic systems where the need/opportunity for system level integration is along the “more than Moore” vector. The "wireless sensor nodes" of the Internet of Things (IoT) is one good example of this emerging trend. The integration challenge in these systems extends beyond logic and SRAM, to include non-volatile memory, embedded analog, RF and power management, high voltage, integrated passives, sensors, actuators and more. The design challenges of power, performance and cost optimization are equally applicable in the context of these systems. While the design size is not as much of a challenge, the heterogeneity requires unique optimization strategies and design verification approaches. One of the challenges, for example, is to drive an optimal system partition and explore chip level versus package level integration tradeoffs. In this talk, we will primarily focus on the low power optimization vector for the "more than Moore" systems and discuss the associated design and verification challenges. View bio >
by Gaurav Jalan, Promotions Chair, DVCon India
The start of DVCon in India is an important milestone. Being a follower of this conference in the US for a long time, it is exciting to realize attending an extension of this event in Bangalore. While the internet and social media bridged the gap to a large extent, still it is far from the experience of witnessing the event in person.
The two-day DVCon India event offers an awesome platform to connect, share and learn at all levels within the fraternity. It starts on September 25th with keynotes from eminent speakers from India and abroad. To address the proliferation of verification and modeling, the event bifurcates into two major tracks: ESL and DV.
Excellent tutorials from industry gurus on widely deployed and emerging topics are a key highlight for the event. With an exorbitant response from the engineers submitting the abstracts for paper and poster sessions, panelists from respective tracks have spent long hours picking the best ones with wide appeal. Apart from the presentations, there is an exhibition from different members of the ecosystem showcasing their products and services while you take a break or enjoy the networking event in the evening.
DVCon India provides an excellent opportunity to showcase, appreciate and celebrate your work, your efforts and your contributions! Come join us as we take the first step towards this exciting journey in the local neighborhood.
DVCon India Quick Links
October 14-15, 2014
DVCon Europe targets the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The conference combines technical paper sessions, tutorials, and an exhibition to bring engineers the latest methodologies, applications and demonstrations on system-level design, verification, IP reuse, design automation, mixed-signal design, low power design, and verification.
DVCon Europe released its Advance Program last week, covering high quality papers, tutorials and posters around best practices and user experiences on design and verification in SystemC, SystemVerilog, PSL, UVM, UPF, IP-XACT, and more.
We encourage you to register early, as Early Registration ends September 12 and space and seating is limited.
Keynote Speaker: Bernd Adler
Wireless CTO & Div. VP Platform Engr. Group
Intel Mobile Communications
Bernd has held the position of RF Chief Scientist and Head of Wireless System Engineering at Intel® Mobile Communications Group Wireless System Engineering activities engineering, line management, product management and site management positions at Infineon Technologies for over 12 years working on cellular transceivers for CDMA, WCDMA, WIMAX and LTE as well as 2G monolithic integration activities paving the way to ultra low cost products. Before this he held RF engineering positions working on modules and oscillators for Base stations. He received his diploma (electrical engineering) in 1989.
Blog: Top 5 Reasons to Visit DVCon Europe
by Oliver Bell, Vice Chair and Tutorial Chair
Why DVCon Europe? This was THE question I had in mind as I was invited last autumn to support this new conference to be held in Munich on Oct 14th and Oct 15th, 2014. Here are my top 5 reasons:
First and foremost, with DVCon Europe we are now able to reach a broader local community, which will benefit of experiencing the latest developments in verification standards and methodologies, without shipping a selected contingent of engineers overseas even in the best of times. A local DVCon event in Europe minimizes overall expenses and it is very encouraging to participate even in times of tight budgets and travel restrictions. Read more >
DVCon Europe Quick Links
March 2-5, 2015
San Jose, California
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