SystemC Evolution Day 2020 Summary

by Ola Dahl, SystemC Evolution Day 2020 Chair

Ola Dahl, SystemC Evolution Day 2020 ChairThe fifth SystemC Evolution Day was held on October 29, 2020. It was a virtual event (a Teams meeting, really) with 111 participants attending two blocks of presentations. The participation was indeed international, with attendees from Europe, North America, and Asia, and we had an approximate 70/30 percentage ratio between Accellera members and non-Accellera members.

We had a 66% participation from user companies, 28% participation from EDA companies, and around 6% representing academic institutions.

The first block of presentations started with a contribution from a team from Raytheon, proposing new TLM extensions for off-chip protocols. The following discussion touched upon topics such as inter-board communication, usage of TLM AT vs. TLM LT, the relation to FMI, and interoperability aspects. A connection to work within the Accellera SystemC Common Practices Subgroup was identified, and ideas for how to continue the discussion were proposed.

Next up was Peter de Jager from Intel, with a presentation on multi-core software debugger connections to SystemC simulators, and possibilities for future standardization in this area. Being a topic that most likely is a part of most virtual platform implementations, it was not difficult to find technical discussion points, such as synchronization issues when using temporal decoupling, and the choice of debug interface, such as gdb which was used in this presentation, vs. e.g. TCF.

An update from SystemC-related Accellera working groups was delivered by Martin Barnasconi, referring to IEEE-standard update work in the SystemC Language Working Group, User Guide and Application Examples releases from the SystemC AMS Working Group, checkpointing and register inspection from the CCI Working Group, a second version of the SystemC Synthesis subset standard and upcoming work on consolidation of SystemC data types from the SystemC Synthesis Working Group, and UVM-SystemC work targeting a UVM-SystemC 1.0 release from the SystemC Verification Working Group, where upcoming work also covers constrained random verification (CRAVE) and functional coverage (FC4SC).

SystemC Evolution Day 2020 User BreakdownAround the European lunch hours, we had opportunities for open discussions. Some of us stayed in the Teams meeting, and others took the opportunity to engage in a more three-dimensional experience, which was possible thanks to a virtual environment, configured and acquired by the DVCon Europe organizing team, and generously shared also with the SystemC Evolution Day participants.

The second block of presentations started with a presentation, and a demonstration, from the Accellera Multi-Language Working group, covering the problem statement, with the need to combine Verification IPs and models implemented in different languages, and describing the proposed Multi-Language Verification architecture, with technical details as well as its support for different use cases, such as VIP re-use.

Mikhail Moiseev from Intel presented a contribution on Temporal Assertions in SystemC. Ways to express temporal assertions in SystemC were described, as well as their corresponding counterparts in SystemVerilog. Use cases and examples, related to High-Level Synthesis, were presented, and an implementation, using the Intel Compiler for SystemC, was described.

The topic of High-Level Synthesis was continued in the next, and last, presentation, where Stuart Swan presented MatchLib, an open source SystemC/C++ library supporting High-Level Synthesis. Examples were described and discussed, covering AXI interconnect design, and simulation experiences, with comparisons of Matchlib results and run-times from SystemC simulations and simulations using HLS-generated RTL.

Having closed the 2020 SystemC Evolution Day, we would like to say a big thank you to all participants and contributors. The SystemC Evolution will (of course!) continue, with a SystemC Evolution Day in 2021, but also with smaller, somewhat regular, events. We will organize these events, which we refer to as Fikas, as smaller, half-day or two-hour, workshops, every quarter. Stay tuned for more information about our Fika events, via the Accellera web site and via regular Accellera communication channels.