Universal Verification Methodology

Universal Verification Methodology (UVM) is a standard to enable guaranteed development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. Accellera provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).

• Validated on multiple simulators
• Scales from block to system level
• Enhanced for multi-language verification
• Standardized as UVM 1.2