Media Coverage
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2024 |
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| November 4th | Notes from DVCon Europe 2024 SemiWiki |
| September 23rd | Accellera Approves Portable Test and Stimulus Standard (PSS) 3.0 Pradeep’s Techpoints |
| September 3rd | Accellera and PSS 3.0 at #61DAC SemiWiki |
| July 18th | System-Level Simulations, Sub-System Digital Twins, 2.5D Heterogeneous Integration, UCIe and CMOS 2.0 Semiconductor Digest |
| April 25th | EDA Looks Beyond Chips Semiconductor Engineering |
| March 21st | Simulating the Whole Car with Multi-Domain Simulation SemiWiki |
| February 29th | Accellera Preps New Standard For Clock-Domain Crossing Semiconductor Engineering |
| January 10th | An Accellera Functional Safety Update SemiWiki |
2023 |
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| November 24th | EDA standards for AI, China eeNews Europe |
| October 31st | DVCon Europe is Coming Soon - Sign Up Now SemiWiki |
| October 26th | Anatomy Of A System Simulation Semiconductor Engineering |
| September 28th | What Happened To Portable Stimulus? Semiconductor Engineering |
| August 2nd | Accellera and Clock Domain Crossing at #60DAC SemiWiki |
| July 13th | CHIPS Act, 3D-IC, AI, Open Source, and EDA-IP Tool Trends Dominate Semiconductor Digest |
| June 29th | Industry Organizations Are the Mainstay of the Semiconductor Ecosystem EE Times Europe |
| May 1st | Speeding the Path to Industry Standardization with Accellera SemiWiki |
| March 16th | Accellera Update at DVCon 2023 SemiWiki |
| January 19th | What’s New in the 2022 IEEE IP-XACT Standard? Big Reveals from the Chair Semiconductor Digest |
| January 13th | Podcast: The International Impact of Accellera’s Work SemiWiki |
2022 |
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| November 23rd | Weighing Chip-Design-Verification Challenges for MedTech EE Times |
| October 4th | Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development Semiconductor Engineering |
| August 10th | DAC – Where RISC-V Thrives and Mixed Signal Design Blends In Electronics Weekly |
| July 29th | Podcast: The History, Reach and Impact of Accellera with Lynn Garibaldi SemiWiki |
| July 6th | Accellera Update: CDC, Safety and AMS SemiWiki |
| April 11th | New Challenges For Connected Vehicles Semiconductor Engineering |
| March 14th | PSS in the Real World Cadence Breakfast Bytes Blogs |
| March 10th | DVCon Functional Safety Cadence Breakfast Bytes Blogs |
| March 2nd | DVCon: UVM Birds of a Feather Cadence Breakfast Bytes Blogs |
| February 8th | Accellera at DVCon U.S. 2022 in the Metaverse! SemiWiki |
| January 11th | Video: Pre-silicon D&V innovation and standardization efforts from Accellera EDACafe Bunker Broadcast |
2021 |
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| December 14th | DAC 2021 – Accellera Panel all about Functional Safety Standards SemiWiki |
| December 9th | Design rules for functional safety are explored at DAC Electronics Weekly |
| September 8th | Functional Safety Working Group Semiconductor Engineering |
| August 11th | Challenges of Transitioning Back from Remote Work to Office Pradeep's Techpoints |
| July 21st | A Hardware Security Standard Advances SemiWiki |
| June 23rd | 5 Verification Engineers Provide Tips to Succeed When Working From Home Design News |
| June 9th | How easy is it building chips during a pandemic? Pradeep's TechPoints |
| May 27th | Accellera Unveils PSS 2.0 – Production Ready SemiWiki |
| May 26th | Functional Safety – What and How SemiWiki |
| May 11th | Accellera’s Functional Safety Group White Paper Semiconductor Engineering |
| April 8th | Interconnects In A Domain-Specific World Semiconductor Engineering |
2020 |
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|---|---|
| December 17th | An Accellera Update. COVID Accelerates Progress SemiWiki |
| October 14th | IP Security Assurance Standard Semiconductor Engineering |
| August 6th | Accellera Tackles Functional Safety Semiconductor Engineering |
| July 23rd | Accellera IP Security Group Expects Standard by Year End Tech Design Forum |
| July 10th | Accellera’s Chair Highlights 2020 Events & Working Group Activity EDACafe, Video Interview |
| May 5th | Accellera Tackles Functional Safety, Mixed-Signal SemiWiki |
| April 14th | What is the Difference Between Test and Verification? Design News |
| March 26th | Standard Evolution Semiconductor Engineering |
| March 26th | Do You Trust Your IP Supplier? Semiconductor Engineering |
| March 20th | Create Once and Test Everywhere: The Promise of Portable Stimulus Design News |
2018 |
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| October 4th | Accellera Tackles IP Security SemiWiki |
| August 8th | Agile Standards Semiconductor Engineering |
| July 6th | EDA Embraces Standard to Streamline IC Test and Verification Electronics Weekly |
| July 2nd | Tools Suppliers Back Version 1.0 of Portable Stimulus Standard Tech Design Forum |
| February 1st | DVCon US 2018 is Bigger and Better EDACafe |
2017 |
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|---|---|
| October 17th | Developing the Portable Stimulus Standard Chip Design |
| August 24th | Portable Stimulus Status Report Semiconductor Engineering |
| March 12th | Celebrating Accellera’s UVM: Now it’s IEEE 1800.2 EDACafe |
| April 27th | Lu Dai: Incoming Accellera Chair SemiWiki |
| February 23rd | Qualcomm’s Lu Dai: Energetic leadership for Accellera EDACafe |
2016 |
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| August 15th | Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License Gabe's EDA |
| July 14th | Shishpal Rawat: Intel, CEDA, Accellera, Calm Commitment EDACafe |
| March 29th | Specs vs. Implementation; Portable Stimulus; Hardware-Software Differences JB Systems |
| March 3rd | Prove It! The New Era of Design Verification Amelia's Weekly Fish Fry |
| January 2016 | SystemVerilog, a Global Success Story, Celebrates 10 Years Speeding Technology to Market IEEE-SA Standards Focus |
2015 |
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| Summer 2015 | Designing Efficiently for a Low Power World EDACafe |
| March 5th | DVCon: The Imitation Game EDACafe |
| February 11th | Accellera Systems Initiative Forms Portable Stimulus Working Group Electronic Engineering Journal |
| February 11th | Accellera Adds Portable Stimulus Group Semiconductor Engineering |
2014 |
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|---|---|
| September 25th | Intel's Shishpal Rawat: Multiple hats, Singular focus EDACafe |
| July 1st | Accellera Updates UVM Standard Semiconductor Engineering |
| June 3rd | Accellera Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard Low-Power Design |
2013 |
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| March 20th | Accellera publishes SystemC-AMS 2.0 standard Tech Design Forum |
| February 25th | DVCon 2013: Engineers Question EDA Standards Leaders at Accellera "Town Hall" Meeting Cadence Industry Insights Blog |
| February 6th | Master & Commander: DVCon's Stan Krolikoski EDACafe |