Community Newsletter: November 2026


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative ChairIt has been a busy summer for Accellera, with great momentum across our standards efforts and events around the world.

Time flies, and it's hard to believe the holiday season is almost upon us! As we approach the end of another productive year, it's a good time to reflect on our accomplishments, recognize the contributions of our community, and look ahead to the opportunities on the horizon.

We have two important events just around the corner that will help us round out the year. DVCon Europe, followed by SystemC Evolution Day, will bring together industry experts, engineers, and researchers to share knowledge, exchange ideas, and explore the latest developments in design and verification. Accellera will have a strong presence at both events, with sessions and announcements highlighting several important standards developments, including the recently approved Functional Safety Language (FSL) 1.0, updates to the Portable Stimulus Standard (PSS) 3.1, and the upcoming public review of SystemC High-Level Synthesis (HLS) Standard 2.0. These developments reflect the continued dedication of our working groups and our commitment to delivering standards that address the evolving needs of the industry.

As we close out the year, I want to extend my sincere appreciation to the many volunteers who make Accellera's work possible. Your expertise, dedication, and enthusiasm are the foundation of our success, and your contributions make a lasting difference to our industry.

I also want to encourage others to become involved. There are many ways to participate in the Accellera community, whether it's attending a DVCon conference, engaging with industry experts through our online forums, providing feedback on draft standards, or taking the first step toward joining a working group. Fresh perspectives and new ideas are always welcome, and there is a place for everyone who wants to contribute to our community and help advance the design and verification industry.

Looking ahead, DVCon U.S. 2027 is just a few months away, taking place March 1-4 in Santa Clara, California. It will be another great opportunity to reconnect with colleagues, learn about emerging technologies, and participate in the conversations shaping the future of design and verification. I hope to see many of you there!

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

News from the Working Groups

A New Milestone in Functional Safety: FSL 1.0 Now Available

Accellera has announced the release of the Functional Safety Language (FSL) Standard 1.0, marking an important advancement in interoperability and automation for functional safety analysis. Developed by Accellera's Functional Safety Working Group, the new standard provides a common language and data model for representing, exchanging, and reusing functional safety information across engineering tools, organizations, and the semiconductor supply chain.

FSL 1.0 addresses the growing complexity of functional safety analysis in automotive, industrial, aerospace, medical, and other safety-critical applications. By standardizing the exchange of Failure Modes, Effects, and Diagnostic Analysis (FMEDA) data, FSL enables greater automation, improved traceability, and reuse of safety information from component to system level. The standard complements existing functional safety standards, including ISO 26262 and IEC 61508, while helping reduce manual effort and improve consistency across design and verification workflows.

FSL 1.0 is available for immediate download. Learn more and access the standard on the Functional Safety Working Group page. For additional insight, watch a short video featuring working group chair Alessandra Nardi, where she discusses the goals and scope of FSL 1.0 and its relationship to other functional safety standards.

PSS 3.1 Now Available: Advancing Verification Portability and Reuse

Portable Stimulus

Accellera has announced the release of the Portable Test and Stimulus Standard (PSS) 3.1, introducing important enhancements that expand verification reuse, improve software integration, and support increasingly complex hardware and software environments. Building on PSS 3.0, the latest release enhances engineers' ability to capture verification intent once and reuse it across simulation, emulation, FPGA prototyping, and post-silicon validation.

PSS 3.1 introduces more expressive constraint modeling, greater flexibility for creating and customizing reusable verification models, and improved control over generated target code. New capabilities also support coordination across heterogeneous execution environments and expand address and register modeling for complex SoCs and embedded systems. Together, these enhancements help engineers improve verification productivity, reduce duplication of effort, and extend the value of verification content across platforms and projects.

PSS 3.1 is available for immediate download. To learn more about PSS and its applications, explore Accellera's 16-part "Learning PSS" video series, along with additional tutorials, examples, and resources available through the Portable Stimulus Working Group page.

SystemC logo

Public Review for SystemC High-Level Synthesis (HLS) Standard 2.0 Coming Soon!

The public review of the SystemC High-Level Synthesis (HLS) Standard 2.0 will open this month. The public review invites the design and verification community to provide feedback on the proposed updates. The latest version expands beyond language syntax to establish a standardized interpretation for high-level synthesis, helping improve consistency and interoperability across HLS tools and design flows.

A key enhancement is the introduction of a new Communication Library that enables throughput-accurate modeling, making it easier for system and hardware designers to model communication behavior at a higher level of abstraction. These improvements aim to simplify HLS design methodologies and support greater productivity and reuse across the industry.

The draft standard will be available for download and public review here. For more information, visit the SystemC Synthesis Working Group page.

 

Upcoming Events

DVCon Europe 2026 logo

DVCon Europe 2026 Showcases Innovation, Research, and Advancements in Standards

DVCon Europe 2026 will take place November 17-18 at the Holiday Inn Munich City Centre in Munich, Germany, bringing together design and verification professionals for two days of technical sessions, tutorials, keynote presentations, exhibits, and networking. This year's keynote speakers will address two important industry challenges: Professor Hussam Amrouch of the Technical University of Munich will explore the relationship between AI and semiconductor innovation, including the growing need for engineering talent, while Antoine Madec, Director of Verification at Axelera AI, will discuss practical approaches to verifying complex ASICs while balancing quality, resources, and time-to-market.

The conference will also feature its dedicated Research Track, which continues to strengthen the connection between academia and industry. Introduced in 2023, the track showcases original, peer-reviewed research addressing emerging challenges in electronic design and verification, including AI and machine learning, system-level design, functional safety, and advanced verification methodologies. Accepted research papers are published through IEEE Xplore, providing greater visibility for new ideas and innovations.

Accellera standards will also be featured in the technical program, including sessions focused on the recently approved Functional Safety Language (FSL) 1.0 and Clock and Reset Domain Crossing (CDC/RDC) Verification Standard 1.0. These sessions will give attendees an opportunity to learn about the latest standards developments and how they address industry challenges in functional safety, interoperability, and design verification. DVCon Europe continues to provide an important forum for sharing practical experience, exploring emerging methodologies, and connecting with the experts advancing electronic design and verification.

Visit the DVCon Europe website to explore the full program and register to attend.

SystemC Evolution Day logo

SystemC Evolution Day 2026: Exploring the Future of SystemC Standards

The 11th annual SystemC Evolution Day will take place November 19, immediately following DVCon Europe, at the Holiday Inn Munich City Centre in Munich, Germany. This full-day technical workshop brings together experts from the SystemC user community and Accellera working groups to explore current and emerging standardization efforts and help shape the future of the SystemC ecosystem.

This year's program will feature updates on SystemC 4.0 standardization, SystemC-AMS, and the public review of SystemC High-Level Synthesis, along with insights from recent SystemC CCI development sprints. Additional sessions will explore practical approaches to SystemC debugging, automotive virtual prototyping, and hands-on implementation of the Federated Simulation Standard (FSS) with SystemC. An open discussion on the use of AI with SystemC will provide another opportunity for attendees to exchange ideas and explore future directions.

Designed as an interactive, user-focused forum, SystemC Evolution Day offers a unique opportunity to engage directly with the experts advancing SystemC standards and contribute to their ongoing development.
Visit the SystemC Evolution Day 2026 page to view the full program and register.

For more information on the SystemC ecosystem, including resources and events, visit SystemC.org.

DVCon U.S. 2027: Four Days of Innovation, Collaboration, and Technical Exchange

DVCon U.S. 2027 logo

DVCon U.S. 2027 will take place March 1–4, 2027, at the Hyatt Regency Santa Clara in Santa Clara, California. Planning is well underway for the four-day conference, with the technical program being finalized to bring together design and verification professionals for keynote presentations, technical papers, tutorials, workshops, panel discussions, exhibits, and networking opportunities.

Jyotika Athavale of Waymo has been announced as the conference's Invited Keynote Speaker. Her presentation, "Safe by Design: Transforming AV Silicon Integration," will explore how the high-performance silicon ecosystem can advance functional safety and hardware dependability through standardized interoperability and advanced on-chip safety mechanisms.

Accellera is also planning technical sessions highlighting its latest standards developments, including presentations from the Clock Domain Crossing and UVM-MS/SystemVerilog-MSI Working Groups. These sessions will provide attendees with an opportunity to learn directly from working group experts and explore emerging design and verification methodologies.

Visit the DVCon U.S. 2027 website for the latest conference updates, program, and registration information.

If you'd like to view proceedings from past DVCon Conferences, visit the DVCon archives site.

 

Portable Stimulus

Explore Accellera's Complete "Learning PSS" Video Series on YouTube

Accellera's 16-part "Learning PSS" video series is now available on YouTube! Presented by Tom Fitzpatrick, PSS expert and charter member of Accellera's Portable Stimulus Working Group, the series takes viewers from the fundamentals of the Portable Stimulus Standard (PSS) through advanced concepts and practical techniques for creating reusable, portable verification models.

Whether you're new to PSS or looking to deepen your understanding, the series provides a valuable resource for learning how to capture verification intent once and reuse it across platforms, abstraction levels, and projects. Watch the complete "Learning PSS" series on YouTube.

 

More Resources

Explore Hundreds of Accellera and DVCon Videos On-Demand

Find the latest videos from our working groups, industry events, and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

IEEE GET Program – Download Standards at No Cost

The IEEE GET Program provides engineers and chip designers worldwide with no cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

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Copyright 2026 Accellera Systems Initiative