Accellera at DAC 2022

Luncheon Panel: "AMS language standards for Design and Verification: Standing still or moving forward?"

DAC 2022Tuesday July 12, 2022
11:45am-1:00pm (room open at 11:30am)
Moscone West Room 3024

Registration for this event is now closed.

We invite you to join us for lunch and a panel discussion focused on the current state of analog/mixed-signal standards, the challenges, and the opportunities. Martin Barnasconi, our Technical Committee Chair, will also provide a brief update on Accellera.

Panel Abstract:
In many application domains such as Communications, Automotive, Biomedical, Aerospace, and Industrial, a solid understanding of analog/RF and mixed-signal concepts is vital to design and verify high quality and robust products. Furthermore, the integration of digital and software technologies in analog- and RF-centric products requires a careful review of the applicability of today’s mixed-signal design, modeling and verification methodologies and flows, and the available tools and languages.

Are today’s AMS language standards sufficient to keep up with the industry needs? What else is required?

The AMS panel will feature industry experts that can shed light on the challenges and opportunities in the mixed-signal design and verification domain and discuss the ongoing standards developments in Accellera on UVM-AMS, SystemC-AMS, and SystemVerilog-AMS as well as available IEEE standards such as SystemVerilog and VHDL-AMS. Panelists will also share their insights into what needs to happen in addition to these initiatives to further advance the mixed-signal design and verification domain.

Have a question for our panelists on AMS standards? We welcome them in advance, and we’ll do our best to address them during the panel discussion. Submit your questions here.

Panelists

Peter GrovePeter Grove
Senior Member of the Technical Staff, Renesas
Accellera SystemVerilog-AMS Working Group Chair
Accellera UVM-AMS Working Group Member

 

Lakshmanan BalasubramanianLakshmanan Balasubramanian
Principal Engineer (Analog Design), MGTS, Texas Instruments, Sr. MIEEE, MIET, CEng.
Accellera UVM-AMS, SystemC-AMS, SystemVerilog-AMS Working Group Member

 

Xiang LiXiang Li
Principal Engineer/Manager, Qualcomm Technologies Inc.
Accellera UVM-AMS Working Group Member

 

Martin Barnasconi Martin Barnasconi
Technical Director System Design & Verification Methodologies, NXP Semiconductors
Accellera SystemC-AMS and IEEE P1666.1 Working Group Chair

 

Nagu DhanwadaNagu Dhanwada
Senior Technical Staff Member, IBM
IEEE P2416 (System Level Power Modeling) Working Group Chair

 

Moderator

Tom FitzpatrickTom Fitzpatrick
Strategic Verification Architect, Siemens EDA
Accellera UVM-AMS Working Group Chair 

 

The Accellera-sponsored luncheon is free to DAC attendees, but registration is required.

 

2022 Global Sponsors

CadenceSiemens EDASynopsys