Community Newsletter: July 2014
IN THIS ISSUE:
- Message from the Chair
DAC Wrap up, UVM, DVCon Europe and India
- Yatin Trivedi Receives 2014 Leadership Award
Recognized for organizational vision, service to standards
- Technical Spotlight: UVM
UVM 1.2 Public Review Open through Oct. 1
- Accellera DAC Report
Accellera Update Video, UVM 1.2 Roundtable Discussion, NASCUG Presentations
- Featured Video Tutorial
OCP: The Journey Continues
- Featured Events
DVCon Europe, DVCon India, DVCon United States
- Accellera in the News
Message from Accellera Systems Initiative Chair
Summertime greetings from Accellera! Standards are heating up with recent activities around UVM and Verilog-AMS and the upcoming DVCon India and DVCon Europe. And you can get involved!
At this year’s Design Automation Conference (DAC), there was a lot of buzz about the Universal Verification Methodology (UVM). UVM improves interoperability and reuse while reducing the overall cost of IP development for each new project. Accellera hosted an expert roundtable discussion to explore the new features in UVM 1.2 standard, migration planning from UVM 1.0 and future enhancements. You can view the slides and listen to the audio on our website. Subsequently we announced the availability of a new version of the class reference document UVM 1.2. We invite you to participate in the UVM 1.2 Public Review Forum open through October 1. This is your opportunity to weigh in on the definition and development of the standard. Find out more about UVM 1.2 in our user community and in the 5,300+ member LinkedIn group.
Also at DAC, Accellera announced the release of the Verilog-AMS 2.4 Language Reference Manual (LRM). Verilog-AMS 2.4 includes extensions to benefit verification, behavioral modeling and compact modeling. The revised LRM and resources are available for download. Work is underway to align Verilog-AMS with the SystemVerilog work of the IEEE 1800 for inclusion of AMS capabilities in a new "SystemVerilog-AMS" standard. Find out more.
Accellera draws heavily from its dedicated volunteers who are passionate about standards. At DAC, we recognized Yatin Trivedi of Synopsys with the 2014 Leadership Award. I would like to personally acknowledge Yatin and thank him for the numerous contributions to Accellera's strategy, promotion, infrastructure and financial management over the years. Read more about Yatin's contributions in this press release.
In the coming months, things really ramp up as DVCon India and DVCon Europe take shape. Check out the informational videos from DVCon India and DVCon Europe for highlights of each conference. We have had significant industry support from each region with several users and vendors giving enthusiastic endorsements. We invite you to attend the conference in the region of your choice and discover the latest in design and verification standards.
I hope you are able to take advantage of the standards and resources available from Accellera. For technical details please visit our technical tutorials and communities.
Enjoy your summer!
Shishpal Rawat, Accellera Systems Initiative Chair
Synopsys' Yatin Trivedi Receives 2014 Leadership Award
Yatin Trivedi, Accellera treasurer and board member, has received the 2014 Accellera Leadership Award. Yatin is recognized for his leadership, organizational and financial vision, and service to the standards industry. The Award is given to an individual who has provided active leadership and contributed significantly in the vision of EDA and IP standards development activities and the governance of Accellera Systems Initiative. Read the press release and find out more about Yatin’s contributions to the industry.
Technical Spotlight: Universal Verification Methodology (UVM)
Just announced is a new version of Accellera’s Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC verification The new version includes enhanced messaging, improvements to the register layer and other features. The reference implementation includes detailed release notes and a script to help users upgrade as some of the new features do introduce backward incompatibility. Find out more.
UVM 1.2 Public Review open through October 1
UVM 1.2 has entered a three-month review period ending October 1, 2014 with a commitment to take the resulting updated UVM 1.2 standard to the IEEE. Users are encouraged to post comments and suggestions using the UVM 1.2 Public Review Forum.
UVM Quick Links
- Download UVM 1.2 and reference implementation
- UVM Community
- Public Review Forum
- UVM LinkedIn Group (over 5,300 members)
- "UVM - What's Now and What's Next." Presented at DVCon 2014. View video tutorial>
- "Lessons from the Trenches: Migrating Legacy Verification Environments to UVM." Presented at DVCon 2013. View video tutorial > View PDF >
- "UVM: Ready, Set, Deploy!" Presented at DVCon 2012. View video tutorial >
Accellera DAC Report
Accellera hosted its annual breakfast and panel discussion during the Design Automation Conference in San Francisco on June 3. A nice group of 80 users, vendors, and educators attended. Accellera Chair Shishpal Rawat presented an update on progress in the standards working groups, the successful IEEE Get program, and the development of the Accellera user communities. Shishpal then presented the Accellera Leadership award to Yatin Trivedi for his organizational and financial contributions and service to Accellera.
View the Accellera Update from Shishpal Rawat >
The panel featured a UVM 1.2 Roundtable with John Aynsley, CTO of Doulos, who engaged panelists Rich Newton, Ericsson, Amol Bhinge, Freescale, Colin McKellar, Imagination, and Mohamed Elmalaki, Intel in a lively discussion on UVM usage, migration planning and potential future enhancements.
Listen to the UVM 1.2 roundtable discussion at DAC >
The North American SystemC Users Group (NASCUG) hosted its 20th meeting. Users from Fraunhofer IIS, Altera, the University of California Irvine, The Hong Kong Polytechnic Institute and CircuitSutra gave technical presentations on topics including UVM and SystemC/SystemC AMS, verification and software virtual platforms, parallel simulation of SystemC models, and high-level synthesis.
View the NASCUG 20 Presentations >
Featured Video Tutorial
"OCP: The Journey Continues" presents the past, present and future of the Open Core Protocol IP interface socket standard, which was transferred to Accellera in October, 2013. This five-part tutorial provides some history and a basic introduction to the OCP Specification itself, and then discusses a variety of topics crucial to the use of OCP in SoC designs: verification IP support, SystemC TLM 2.0 support and IP-XACT support. The tutorial closes with a discussion of future needs in IP core interfacing and where future version of the OCP standard may play a role.
Also recently available:
- "Experience the Next ~Wave~ of Analog and Digital Signal Processing using SystemC AMS 2.0"
- "UVM — What's Now and What's Next"
September 25-26, 2014
Call for tutorials open through August 4
Video highlights >
October 14-15, 2014
Program at a glance >
Registration now open >
DVCon United States
March 2-5, 2015
San Jose, California
Call for abstracts open through August 28
Accellera in the News
Accellera Systems Initiative Releases UVM 1.2
24 June 2014 — Accellera announced it released a new version of its Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC (system on chip) verification. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. Read the press release.
Accellera Systems Initiative Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard
June 3, 2014 — Accellera announced it has developed new verification and design modeling extensions for its Verilog-AMS standard. Verilog-AMS provides powerful structural and behavioral modeling capabilities for mixed-signal designs. The revised language reference manual is available for download under open source license. Read the press release.
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