DVCon India 2016: A Success in the Making

by Gabe Moretti
August 23, 2016

The third edition of DVCon India will be held September 15 and 16 at the Leela Palace hotel in Bangalore. Accellera System Initiative, the conference sponsor, is continuing to enlarge its community of professionals by bringing to India a unique opportunity for engineers at all levels to learn, share, and network. Traveling costs are so high in comparison to the registration and hotel costs to make it impractical for Indian engineers to travel to San Jose to attend the original DVCon every year. By sponsoring local DVCon conferences in India and Europe so far, and in China beginning next year, Accellera demonstrates its interest in serving design and verification professionals worldwide.

During the two days, participants in DVCon India will have the opportunity to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions and exhibits from ecosystem partners.   Of course there will also be the opportunity to become familiar with the various working groups in Accellera and decide to become an active participant in the development of industry standards that have a high probability to become IEEE standards. Examples of such standards include UVM, SystemC (and its variants like SystemC-AMS, SCV, CCI, Synthesis subset), SystemVerilog, PSL, Assertions for AMS, Verilog, IP-XACT, OCP and many more.  An Accellera working group that is attracting high levels of interest at this time is Portable Stimulus. You can start to familiarize yourself with this topic by attending the tutorial on Thursday, September 15 at 2:00 PM.

The conference General Chair, Gaurav Jalan, from Aricent, in his welcome message comments on the changing requirements of our industry. "Today, the semiconductor industry is experiencing a major change in its landscape. Post the PC & mobile era, all eyes are on IoT which is an ecosystem of interconnected devices that are high on performance, low on power consumption, cheap and highly customized to the end user expectations. This requires a paradigm shift in how we design products enabling first silicon success faster than ever before. Starting from the concept exploration at the system level and bringing it down to the IPs interconnected on the SoC, DVCon India touches different aspects of design and verification. The discussions and information exchange covers a wide variety of topics, representing the latest developments and future trends in this domain."

The conference will offer two tracks, an ESL and a Design and Verification (DV) track. Attendees can choose at will and attend any sessions they are interested in. The ESL track will focus on SystemC related topics such as Pre-Si SW development and debug using virtual prototypes of electronic systems and SoCs, architectural exploration, power and performance analysis for use cases, high level synthesis, model interoperable standards and more. The DV track topics cover Design and Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation tools and more.

Throughout the conference a number of keynote speeches will provide a panoramic view of the state and opportunities of our industry. Wally Rhines, who needs no introduction, will talk about "Design Verification: Challenging Yesterday, Today and Tomorrow." Design verification methodologies are in an endless race to catch up with exploding verification needs. As soon as the verification industry standardizes on a methodology, a new set of requirements emerges. Dr. Rhines will review the major phases of the verification evolution over the past several decades and then focus on the challenges of newly emerging problems. Functional verification still is a primary concern, but new requirements for security and safety are becoming more important and could ultimately pose challenges more daunting than those we have faced in the past. Kamakoti Veezhinathan, of the Indian Institute of Technology in Madras, will talk about the Indian government's "Make in India" initiative. There are many major drives of this initiative on electronic systems. Needless to say that computation and communication are the critical and primary areas where electronic systems are deployed. Keeping the broad picture in mind, the work at RISE LAB-IIT-Madras has come up with a Secure Computation and Communication framework. The framework and its components are envisaged, designed, developed and tested at RISE LAB CSE Department IIT Madras, thus making it a true "Make in India" initiative.

Subrangshu Das, Canon India Pvt.Ltd, will deliver a talk with the title of "Microprocessors to Smartphones to Autonomous Cars to Deep Learning" in the ESL track. And in the DV track Alok Jain from Cadence will cover "Verification for Complex SoC's."  And all this in just the first four hours of the conference!

Two more keynotes are scheduled for Friday. One of them is in the process of being finalized as this article was issued, with details available soon. The other, by Sushil Gupta of Synopsys is titled:  "Today's SoC Verification Challenges: Mobile and Beyond."

Each track will also offer a panel. In the ESL track the topic is "An Entry Level Vehicle for IoT Market Space" while in the DV track the topic to be discussed is: "The Future Verification Flow."

I counted 17 paper sessions during the two days, divided between ESL and DV topics. A great opportunity to learn and to see what your colleagues are working on. Speaking of learning, the conference offers 11 tutorial sessions covering issues in both ESL and DV tracks.

The exhibit area is also growing. The floor space is filling up quickly with just a few weeks to go before the opening speech. So attendees will have the opportunity to see the latest tools and methods to help them in their challenging work.

To learn the details of the conference agenda, the exhibit, the hotel and the registration details go to the conference web site: dvcon-india.org. I wish I could say "I will see you there" but those travel costs...